Cypress Semiconductor /psoc63 /CSD0 /SEQ_START

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Interpret as SEQ_START

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (SEQ_MODE)SEQ_MODE 0 (ABORT)ABORT 0 (DSI_START_EN)DSI_START_EN 0 (AZ0_SKIP)AZ0_SKIP 0 (AZ1_SKIP)AZ1_SKIP

Description

Sequencer start

Fields

START

Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode).

SEQ_MODE

0 = regular CSD scan + optional ADC 1 = coarse initialization, the Sequencer will go to the INIT_COARSE state.

ABORT

When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0.

DSI_START_EN

When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer.

AZ0_SKIP

When set the AutoZero_0 state will be skipped

AZ1_SKIP

When set the AutoZero_1 state will be skipped

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